1. Field of the Invention
The present invention relates to a memory device capable of enhancing the access speed and access efficiency of a volatile/large capacity semiconductor memory LSI represented by a dynamic random access memory (DRAM) or the like.
2. Description of the Related Art
In a volatile/large capacity semiconductor memory, particularly, a dynamic random access memory (DRAM), a minute electric potential difference made between two pairs of signal lines (bit lines) to which the data input-output of a memory cell is connected is amplified by a sense amplifier, thereby reading data and rewriting the data broken during the reading. Furthermore, it is necessary to perform an operation (precharging) for setting the bit line pairs to have the same electric potential before the reading operation in order to obtain a minute electric potential difference. Therefore, a speed is generally increased with difficulty.
For example, the speed increasing technique of the volatile/large capacity semiconductor memory having the above-mentioned properties has been disclosed in the Document 1 "Shigetoshi Wakayama et al., "10-ns Row Cycle DRAM using Temporal Data Storage Buffer Architecture," 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp. 12-15".
The technique disclosed in the Document 1 will be described below with reference to FIGS. 1 and 2. A memory cell 5 is arranged in a matrix to form a memory cell array 6. A word line 1 is connected to a gate of each memory cell 5. A precharge circuit 14 is controlled by a precharge signal 15, thereby initializing a bit line pair 12 to have the same electric potential. Thus, each memory cell 5 is precharged. The bit line pair 12 is connected to a sense amplifier (SA) 81 through a transfer gate 80, and a data line pair 13 is connected to the sense amplifier 81. The transfer gate 80 is controlled by a SA selecting signal 82, and the sense amplifier 81 is controlled by a SA activating signal 83.
In the technique thus disclosed, a minute electric potential difference made in the bit line pair 12 is amplified by the sense amplifier 81, thereby reading data. However, when the minute electric potential difference is made on the sense amplifier, a connection between the memory cell 5 and the sense amplifier 81 is cut off by using the transfer gate 80.
Consequently, the data in the broken memory cell is not rewritten. However, the bit line pair 12 having a high load is separated. Consequently, the amplification time of the sense amplifier 81 is shortened to increase a reading speed.
Moreover, another prior art has been disclosed in the Document 2 "Katsumi Dosaka et al., "A 100 MHz 4 MHz 4 Mb Cache DRAM with Fast Copy-Back Scheme," 1992 ISSCC Digest of Technical Papers, pp. 148-149". The technique (second prior art) described in the Document 2 will be described below ith reference to FIG. 3. In FIG. 3, the reference numerals 90 and 91 denote a SA selecting signal, the reference numerals 92 and 93 denote a SA activating signal, and the reference numerals 96 and 99 denote a bit line pair.
In this technique, as shown in FIG. 3, an amplifier (SA) 95 having a read data holding function and a write buffer (WB) 98 having a write data holding function are separately provided and are connected to the bit line pair 12 through an amplifier selecting switch 94 and a write buffer selecting switch 97, respectively.
In such a structure, the reading operation is carried out by first selecting the memory cell 5 by the word line 1 and then bringing the amplifier selecting switch 94 into a conductive state, thereby making a minute electric potential difference on the bit line pair 12 and the amplifier (RA) 95 having a read data holding function. Next, the minute electric potential difference is amplified by the amplifier (RA) 95 having a read data holding function, thereby reading data on a reading data output line 96 and rewriting the data into the memory cell.
On the other hand, the writing operation is carried out by temporarily holding data input from a writing data input line 99 in the write buffer (WB) 98 having a write data holding function. For a period in which the reading is not required, then, the memory cell is selected by the word line 1, thereby bringing the write buffer selecting switch into a conductive state to perform the writing. Therefore, a writing operation period can have flexibility by temporarily holding the write data. Thus, the writing operation can be hidden for a period in which the reading operation is not performed and can be therefore carried out easily. Consequently, the delay of a reading operation start time for the writing operation can be reduced. As a result, high-speed access can be carried out.
Although the reading speed can be increased and the delay time of the reading operation start period for the writing operation can be reduced in the above-mentioned conventional memory device, there has been the following problem.
In a processing to treat large capacity data which is represented by an image processing, so-called read-modify-write is frequently carried out, that is, data read from a memory device is processed and is immediately written to the memory device. In such a read-write manner, the reading and writing operations for the memory device are generated with almost the same frequency.
In the technique disclosed in the Document 1, accordingly, the reading speed can be increased but the writing speed cannot be increased. Therefore, the technique cannot cope with the read-modify-write. Moreover, the technique disclosed in the Document 2 is effective in the case where the reading frequency is greater than the writing frequency. However, in the case where the technique is applied to the read-modify-write in which the reading and writing operations are performed with almost the same frequencies, the writing operation cannot be hidden for the period in which the reading operation is not carried out. Therefore, the read-write cannot be performed at a high speed.
In the conventional memory device, thus, there has been a problem in that the delay time of the reading operation start period by the writing operation cannot be reduced in the case where the writing frequency and the reading frequency are almost equal to each other in order to increase a reading speed.